Recent technological trends in flash media have made it an attractive alternative for data storage in a wide spectrum of computing devices such as PDA's, mobile phones, embedded sensors, MP3 players, etc. The success of flash media for these devices is due mainly to its superior characteristics such as smaller size, lighter weight, better shock resistance, lower power consumption, less noise, and faster read performance than disk drives. While flash-memory has been the primary storage media for embedded devices, there is an increasing trend that flash memory will infiltrate the personal computer market segment. As its capacity increases and price drops, flash media can overcome adoption as compared with lower-end, lower-capacity magnetic disk drives.
NAND devices are generally manufactured and produced to be as simple and inexpensive as possible. Because of the low-cost demands for NAND flash, there is typically no resource applied to validating whether or not a command presented to the NAND flash is correct or in the best interest of the data contained in the flash part itself before it is processed; stated bluntly they are “dumb” devices. This poses a very real problem for storage devices that must meet certain expectations with respect to data protection.
The fabrication processes for NAND devices has traditionally not allowed for types of constructs that would make it easy to add embedded processing/checking power to the NAND device, thus there are only the simplest of state machines incorporated for processing NAND commands on the NAND device. Thus, it is up to the NAND controller to ensure the data integrity of the user data stored on the part. NAND controllers, however, are not “fool proof” given that errors in the NAND memory, firmware, or other components, can cause an otherwise correct controller command sequence to become an erroneous sequence. This erroneous sequence can cause the loss of user data.
Generally, the usefulness of a NAND device can be based on how long data can be written and then correctly read data from the NAND device. For NAND flash, each program/erase cycle increases the likelihood that there will be bit errors when the data is read back from the device. Since there is a likelihood that the data will need to be corrected when read back, there is typically a minimum amount of error correcting code (ECC) that is specified in the NAND datasheet to satisfy the correction requirements likely to be needed for the stated program/erase cycle range.
The prediction of End of Life (EOL) for solid state storage can be a critical operation to ensure continuing reliable operation of a NAND device. With current practices, a NAND device's EOL can be determined by tracking and comparing the number of erase cycles a NAND block has to an arbitrary pre-established maximum and providing a notification when the tabulated count is within a certain distance of the pre-calculated maximum.
It is appreciated from the foregoing that there exists a need for systems and methods to overcome the shortcomings of existing NAND architectures.